//                                                                             
// File:       ./chn_table_map.vrh                                             
// Creator:    tyzhang                                                         
// Time:       Friday Jul 20, 2012 [3:33:29 pm]                                
//                                                                             
// Path:       /localtrees/tianfang/tianfang_lt_depot/chips/rome/dev/doc/headers/wl_soc_mac
// Arguments:  /cad/denali/blueprint/3.7.4//Linux-64bit/blueprint -odir .      
//             -codegen ath_vrh.codegen -ath_vrh -Wdesc ./chn_table_map.rdl    
//                                                                             
// Sources:    /localtrees/tianfang/tianfang_lt_depot/chips/rome/dev/doc/ip/R1_IP5/rtl/bb_2x2/blueprint/chn_table_map.rdl
//             /localtrees/tianfang/tianfang_lt_depot/chips/rome/dev/env/blueprint/ath_vrh.pm
//             /cad/local/lib/perl/Pinfo.pm                                    
//                                                                             
// Blueprint:   3.7.4 (Fri Jan 9 05:41:17 PST 2009)                            
// Machine:    qing                                                            
// OS:         Linux 2.6.9-89.ELsmp                                            
// Description:                                                                
//                                                                             
// No Description Provided                                                     
//                                                                             
//                                                                             


#ifndef _CHN_TABLE_MAP_H_
#define _CHN_TABLE_MAP_H_
// 0x0080 (BB_PAPRD_POWER_AT_AM2AM_CAL_B0)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_MSB 29
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_LSB 24
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_MASK 0x3f000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_4_B0_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_MSB 23
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_LSB 18
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_MASK 0x00fc0000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_3_B0_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_MSB 17
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_LSB 12
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_MASK 0x0003f000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_2_B0_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_MSB 11
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_LSB 6
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_MASK 0x00000fc0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_1_B0_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_MSB 5
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_LSB 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_MASK 0x0000003f
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_PAPRD_POWER_AT_AM2AM_CAL_0_B0_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_ADDRESS                       0x0080
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_HW_MASK                       0x3fffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_SW_MASK                       0x3fffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_HW_WRITE_MASK                 0x00000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_SW_WRITE_MASK                 0x3fffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_RSTMASK                       0xc0000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B0_RESET                         0x00000000

// 0x0084 (BB_PAPRD_VALID_OBDB_B0)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_MSB             29
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_LSB             24
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_MASK            0x3f000000
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_MASK) >> BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_LSB)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_LSB) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_MASK)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_4_B0_RESET           63
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_MSB             23
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_LSB             18
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_MASK            0x00fc0000
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_MASK) >> BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_LSB)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_LSB) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_MASK)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_3_B0_RESET           63
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_MSB             17
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_LSB             12
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_MASK            0x0003f000
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_MASK) >> BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_LSB)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_LSB) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_MASK)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_2_B0_RESET           63
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_MSB             11
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_LSB             6
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_MASK            0x00000fc0
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_MASK) >> BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_LSB)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_LSB) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_MASK)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_1_B0_RESET           63
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_MSB             5
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_LSB             0
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_MASK            0x0000003f
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_MASK) >> BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_LSB)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_LSB) & BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_MASK)
#define BB_PAPRD_VALID_OBDB_B0_PAPRD_VALID_OBDB_0_B0_RESET           63
#define BB_PAPRD_VALID_OBDB_B0_ADDRESS                               0x0084
#define BB_PAPRD_VALID_OBDB_B0_HW_MASK                               0x3fffffff
#define BB_PAPRD_VALID_OBDB_B0_SW_MASK                               0x3fffffff
#define BB_PAPRD_VALID_OBDB_B0_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_VALID_OBDB_B0_SW_WRITE_MASK                         0x3fffffff
#define BB_PAPRD_VALID_OBDB_B0_RSTMASK                               0xffffffff
#define BB_PAPRD_VALID_OBDB_B0_RESET                                 0x3fffffff

// 0x0100 (BB_CHN_TABLES_DUMMY_2)
#define BB_CHN_TABLES_DUMMY_2_DUMMY2_MSB                             31
#define BB_CHN_TABLES_DUMMY_2_DUMMY2_LSB                             0
#define BB_CHN_TABLES_DUMMY_2_DUMMY2_MASK                            0xffffffff
#define BB_CHN_TABLES_DUMMY_2_DUMMY2_GET(x)                          (((x) & BB_CHN_TABLES_DUMMY_2_DUMMY2_MASK) >> BB_CHN_TABLES_DUMMY_2_DUMMY2_LSB)
#define BB_CHN_TABLES_DUMMY_2_DUMMY2_SET(x)                          (((0 | (x)) << BB_CHN_TABLES_DUMMY_2_DUMMY2_LSB) & BB_CHN_TABLES_DUMMY_2_DUMMY2_MASK)
#define BB_CHN_TABLES_DUMMY_2_DUMMY2_RESET                           0
#define BB_CHN_TABLES_DUMMY_2_ADDRESS                                0x0100
#define BB_CHN_TABLES_DUMMY_2_HW_MASK                                0xffffffff
#define BB_CHN_TABLES_DUMMY_2_SW_MASK                                0xffffffff
#define BB_CHN_TABLES_DUMMY_2_HW_WRITE_MASK                          0x00000000
#define BB_CHN_TABLES_DUMMY_2_SW_WRITE_MASK                          0xffffffff
#define BB_CHN_TABLES_DUMMY_2_RSTMASK                                0x00000000
#define BB_CHN_TABLES_DUMMY_2_RESET                                  0x00000000

// 0x0890 (BB_TXIQCORR_TXPATH_COEF_B0_0)
#define BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_MSB   17
#define BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_LSB   0
#define BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_MASK  0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_GET(x) (((x) & BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_MASK) >> BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_LSB)
#define BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_SET(x) (((0 | (x)) << BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_LSB) & BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_MASK)
#define BB_TXIQCORR_TXPATH_COEF_B0_0_TXIQCORR_TXPATH_COEF_CHN0_RESET 0
#define BB_TXIQCORR_TXPATH_COEF_B0_0_ADDRESS                         0x0890
#define BB_TXIQCORR_TXPATH_COEF_B0_ADDRESS                           BB_TXIQCORR_TXPATH_COEF_B0_0_ADDRESS
#define BB_TXIQCORR_TXPATH_COEF_B0_0_HW_MASK                         0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B0_0_SW_MASK                         0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B0_0_HW_WRITE_MASK                   0x00000000
#define BB_TXIQCORR_TXPATH_COEF_B0_0_SW_WRITE_MASK                   0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B0_0_RSTMASK                         0xffffffff
#define BB_TXIQCORR_TXPATH_COEF_B0_0_RESET                           0x00000000

// Skip 894 (BB_TXIQCORR_TXPATH_COEF_B0_1) - 8cc (BB_TXIQCORR_TXPATH_COEF_B0_15) for brevity
// 0x08d0 (BB_TXIQCORR_RXPATH_COEF_B0_0)
#define BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_MSB   17
#define BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_LSB   0
#define BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_MASK  0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_GET(x) (((x) & BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_MASK) >> BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_LSB)
#define BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_SET(x) (((0 | (x)) << BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_LSB) & BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_MASK)
#define BB_TXIQCORR_RXPATH_COEF_B0_0_TXIQCORR_RXPATH_COEF_CHN0_RESET 0
#define BB_TXIQCORR_RXPATH_COEF_B0_0_ADDRESS                         0x08d0
#define BB_TXIQCORR_RXPATH_COEF_B0_ADDRESS                           BB_TXIQCORR_RXPATH_COEF_B0_0_ADDRESS
#define BB_TXIQCORR_RXPATH_COEF_B0_0_HW_MASK                         0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B0_0_SW_MASK                         0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B0_0_HW_WRITE_MASK                   0x00000000
#define BB_TXIQCORR_RXPATH_COEF_B0_0_SW_WRITE_MASK                   0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B0_0_RSTMASK                         0xffffffff
#define BB_TXIQCORR_RXPATH_COEF_B0_0_RESET                           0x00000000

// Skip 8d4 (BB_TXIQCORR_RXPATH_COEF_B0_1) - 90c (BB_TXIQCORR_RXPATH_COEF_B0_15) for brevity
// 0x0910 (BB_RXIQCORR_RXPATH_COEF_B0_0)
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_MSB   17
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_LSB   0
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_MASK  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_MASK) >> BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_LSB)
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_LSB) & BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_MASK)
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RXIQCORR_RXPATH_COEF_CHN0_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_B0_0_ADDRESS                         0x0910
#define BB_RXIQCORR_RXPATH_COEF_B0_ADDRESS                           BB_RXIQCORR_RXPATH_COEF_B0_0_ADDRESS
#define BB_RXIQCORR_RXPATH_COEF_B0_0_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B0_0_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B0_0_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_B0_0_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_B0_0_RESET                           0x00000000

// Skip 914 (BB_RXIQCORR_RXPATH_COEF_B0_1) - 94c (BB_RXIQCORR_RXPATH_COEF_B0_15) for brevity
// 0x0950 (BB_RXIQCORR_TXPATH_COEF_B0_0)
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_MSB   17
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_LSB   0
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_MASK  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_MASK) >> BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_LSB)
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_LSB) & BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_MASK)
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RXIQCORR_TXPATH_COEF_CHN0_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_B0_0_ADDRESS                         0x0950
#define BB_RXIQCORR_TXPATH_COEF_B0_ADDRESS                           BB_RXIQCORR_TXPATH_COEF_B0_0_ADDRESS
#define BB_RXIQCORR_TXPATH_COEF_B0_0_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B0_0_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B0_0_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_B0_0_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_B0_0_RESET                           0x00000000

// Skip 954 (BB_RXIQCORR_TXPATH_COEF_B0_1) - 98c (BB_RXIQCORR_TXPATH_COEF_B0_15) for brevity
// 0x0990 (BB_RXCAL_TX_GAIN_TABLE_B0_0)
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_MSB     19
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_LSB     0
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_MASK    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_GET(x)  (((x) & BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_MASK) >> BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_SET(x)  (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_LSB) & BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RXCAL_TX_GAIN_TABLE_CHN0_RESET   0
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_ADDRESS                          0x0990
#define BB_RXCAL_TX_GAIN_TABLE_B0_ADDRESS                            BB_RXCAL_TX_GAIN_TABLE_B0_0_ADDRESS
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_B0_0_RESET                            0x00000000

// Skip 994 (BB_RXCAL_TX_GAIN_TABLE_B0_1) - a0c (BB_RXCAL_TX_GAIN_TABLE_B0_31) for brevity
// 0x0a10 (BB_RXCAL_RX_GAIN_TABLE_1_0_B0)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_1_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RXCAL_RX_GAIN_TABLE_0_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_ADDRESS                        0x0a10
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B0_RESET                          0x00000000

// 0x0a14 (BB_RXCAL_RX_GAIN_TABLE_3_2_B0)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_3_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RXCAL_RX_GAIN_TABLE_2_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_ADDRESS                        0x0a14
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B0_RESET                          0x00000000

// 0x0a18 (BB_RXCAL_RX_GAIN_TABLE_5_4_B0)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_5_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RXCAL_RX_GAIN_TABLE_4_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_ADDRESS                        0x0a18
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B0_RESET                          0x00000000

// 0x0a1c (BB_RXCAL_RX_GAIN_TABLE_7_6_B0)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_7_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RXCAL_RX_GAIN_TABLE_6_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_ADDRESS                        0x0a1c
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B0_RESET                          0x00000000

// 0x0a20 (BB_RXCAL_RX_GAIN_TABLE_9_8_B0)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_9_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RXCAL_RX_GAIN_TABLE_8_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_ADDRESS                        0x0a20
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B0_RESET                          0x00000000

// 0x0a24 (BB_RXCAL_RX_GAIN_TABLE_11_10_B0)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_11_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RXCAL_RX_GAIN_TABLE_10_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_ADDRESS                      0x0a24
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_HW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_SW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_SW_WRITE_MASK                0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RSTMASK                      0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B0_RESET                        0x00000000

// 0x0a28 (BB_RXCAL_RX_GAIN_TABLE_13_12_B0)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_13_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RXCAL_RX_GAIN_TABLE_12_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_ADDRESS                      0x0a28
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_HW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_SW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_SW_WRITE_MASK                0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RSTMASK                      0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B0_RESET                        0x00000000

// 0x0a2c (BB_RXCAL_RX_GAIN_TABLE_15_14_B0)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_15_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_MASK) >> BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_LSB) & BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RXCAL_RX_GAIN_TABLE_14_CHN0_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_ADDRESS                      0x0a2c
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_HW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_SW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_SW_WRITE_MASK                0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RSTMASK                      0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B0_RESET                        0x00000000

// 0x0a30 (BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_ADDRESS                  0x0a30
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_HW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_SW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_HW_WRITE_MASK            0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_SW_WRITE_MASK            0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RSTMASK                  0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B0_RESET                    0x00000000

// 0x0a34 (BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_ADDRESS                  0x0a34
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_HW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_SW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_HW_WRITE_MASK            0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_SW_WRITE_MASK            0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RSTMASK                  0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B0_RESET                    0x00000000

// 0x0a38 (BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_ADDRESS                 0x0a38
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_HW_MASK                 0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_SW_MASK                 0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_HW_WRITE_MASK           0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_SW_WRITE_MASK           0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RSTMASK                 0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B0_RESET                   0x00000000

// 0x0a3c (BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN0_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_ADDRESS                0x0a3c
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_HW_MASK                0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_SW_MASK                0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_HW_WRITE_MASK          0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_SW_WRITE_MASK          0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RSTMASK                0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B0_RESET                  0x00000000

// 0x0a40 (BB_RXCAL_TX_IQCORR_IDX_7_0_B0)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_7_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_6_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_5_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_4_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_3_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_2_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_1_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RXCAL_TX_IQCORR_IDX_0_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_ADDRESS                        0x0a40
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_HW_MASK                        0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_SW_MASK                        0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_SW_WRITE_MASK                  0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RSTMASK                        0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B0_RESET                          0x00000000

// 0x0a44 (BB_RXCAL_TX_IQCORR_IDX_15_8_B0)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_15_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_14_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_13_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_12_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_11_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_10_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_9_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RXCAL_TX_IQCORR_IDX_8_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_ADDRESS                       0x0a44
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_HW_MASK                       0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_SW_MASK                       0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_HW_WRITE_MASK                 0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_SW_WRITE_MASK                 0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RSTMASK                       0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B0_RESET                         0x00000000

// 0x0a48 (BB_RXCAL_TX_IQCORR_IDX_23_16_B0)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_23_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_22_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_21_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_20_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_19_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_18_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_17_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RXCAL_TX_IQCORR_IDX_16_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_ADDRESS                      0x0a48
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_HW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_SW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_SW_WRITE_MASK                0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RSTMASK                      0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B0_RESET                        0x00000000

// 0x0a4c (BB_RXCAL_TX_IQCORR_IDX_31_24_B0)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_31_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_30_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_29_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_28_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_27_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_26_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_25_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RXCAL_TX_IQCORR_IDX_24_CHN0_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_ADDRESS                      0x0a4c
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_HW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_SW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_SW_WRITE_MASK                0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RSTMASK                      0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B0_RESET                        0x00000000

// 0x0a50 (BB_TXCAL_RX_IQCORR_IDX_7_0)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_MSB         31
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_LSB         28
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_MASK        0xf0000000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_7_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_MSB         27
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_LSB         24
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_MASK        0x0f000000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_6_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_MSB         23
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_LSB         20
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_MASK        0x00f00000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_5_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_MSB         19
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_LSB         16
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_MASK        0x000f0000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_4_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_MSB         15
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_LSB         12
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_MASK        0x0000f000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_3_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_MSB         11
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_LSB         8
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_MASK        0x00000f00
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_2_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_MSB         7
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_LSB         4
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_MASK        0x000000f0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_1_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_MSB         3
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_LSB         0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_MASK        0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_MASK) >> BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_LSB) & BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_7_0_TXCAL_RX_IQCORR_IDX_0_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_7_0_ADDRESS                           0x0a50
#define BB_TXCAL_RX_IQCORR_IDX_7_0_HW_MASK                           0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_7_0_SW_MASK                           0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_7_0_HW_WRITE_MASK                     0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_SW_WRITE_MASK                     0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_7_0_RSTMASK                           0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_7_0_RESET                             0x00000000

// 0x0a54 (BB_TXCAL_RX_IQCORR_IDX_15_8)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_MSB       31
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_LSB       28
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_MASK      0xf0000000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_GET(x)    (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_SET(x)    (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_15_RESET     0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_MSB       27
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_LSB       24
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_MASK      0x0f000000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_GET(x)    (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_SET(x)    (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_14_RESET     0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_MSB       23
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_LSB       20
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_MASK      0x00f00000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_GET(x)    (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_SET(x)    (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_13_RESET     0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_MSB       19
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_LSB       16
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_MASK      0x000f0000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_GET(x)    (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_SET(x)    (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_12_RESET     0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_MSB       15
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_LSB       12
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_MASK      0x0000f000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_GET(x)    (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_SET(x)    (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_11_RESET     0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_MSB       11
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_LSB       8
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_MASK      0x00000f00
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_GET(x)    (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_SET(x)    (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_10_RESET     0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_MSB        7
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_LSB        4
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_MASK       0x000000f0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_GET(x)     (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_SET(x)     (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_9_RESET      0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_MSB        3
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_LSB        0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_MASK       0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_GET(x)     (((x) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_MASK) >> BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_SET(x)     (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_LSB) & BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_15_8_TXCAL_RX_IQCORR_IDX_8_RESET      0
#define BB_TXCAL_RX_IQCORR_IDX_15_8_ADDRESS                          0x0a54
#define BB_TXCAL_RX_IQCORR_IDX_15_8_HW_MASK                          0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_15_8_SW_MASK                          0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_15_8_HW_WRITE_MASK                    0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_SW_WRITE_MASK                    0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_15_8_RSTMASK                          0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_15_8_RESET                            0x00000000

// 0x0a58 (BB_TXCAL_RX_IQCORR_IDX_23_16)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_MSB      31
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_LSB      28
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_MASK     0xf0000000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_23_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_MSB      27
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_LSB      24
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_MASK     0x0f000000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_22_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_MSB      23
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_LSB      20
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_MASK     0x00f00000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_21_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_MSB      19
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_LSB      16
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_MASK     0x000f0000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_20_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_MSB      15
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_LSB      12
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_MASK     0x0000f000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_19_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_MSB      11
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_LSB      8
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_MASK     0x00000f00
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_18_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_MSB      7
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_LSB      4
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_MASK     0x000000f0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_17_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_MSB      3
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_LSB      0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_MASK     0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_GET(x)   (((x) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_MASK) >> BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_SET(x)   (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_LSB) & BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_23_16_TXCAL_RX_IQCORR_IDX_16_RESET    0
#define BB_TXCAL_RX_IQCORR_IDX_23_16_ADDRESS                         0x0a58
#define BB_TXCAL_RX_IQCORR_IDX_23_16_HW_MASK                         0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_23_16_SW_MASK                         0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_23_16_HW_WRITE_MASK                   0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_SW_WRITE_MASK                   0xffffffff
#define BB_TXCAL_RX_IQCORR_IDX_23_16_RSTMASK                         0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_23_16_RESET                           0x00000000

// 0x0a5c (BB_TXCAL_RX_IQCORR_IDX_24)
#define BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_MSB         3
#define BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_LSB         0
#define BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_MASK        0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_GET(x)      (((x) & BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_MASK) >> BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_LSB)
#define BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_SET(x)      (((0 | (x)) << BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_LSB) & BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_MASK)
#define BB_TXCAL_RX_IQCORR_IDX_24_TXCAL_RX_IQCORR_IDX_24_RESET       0
#define BB_TXCAL_RX_IQCORR_IDX_24_ADDRESS                            0x0a5c
#define BB_TXCAL_RX_IQCORR_IDX_24_HW_MASK                            0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_24_SW_MASK                            0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_24_HW_WRITE_MASK                      0x00000000
#define BB_TXCAL_RX_IQCORR_IDX_24_SW_WRITE_MASK                      0x0000000f
#define BB_TXCAL_RX_IQCORR_IDX_24_RSTMASK                            0xfffffff0
#define BB_TXCAL_RX_IQCORR_IDX_24_RESET                              0x00000000

// 0x0a60 (BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_MSB    29
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_LSB    20
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_MASK   0x3ff00000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_2_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_MSB    19
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_LSB    10
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_MASK   0x000ffc00
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_1_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_MSB    9
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_LSB    0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_MASK   0x000003ff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_PAPRD_SM_SIG_GAIN_0_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_ADDRESS                    0x0a60
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_HW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_SW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_HW_WRITE_MASK              0x00000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_SW_WRITE_MASK              0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_RSTMASK                    0xc0000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B0_RESET                      0x00000000

// 0x0a64 (BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_MSB    29
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_LSB    20
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_MASK   0x3ff00000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_5_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_MSB    19
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_LSB    10
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_MASK   0x000ffc00
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_4_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_MSB    9
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_LSB    0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_MASK   0x000003ff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_PAPRD_SM_SIG_GAIN_3_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_ADDRESS                    0x0a64
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_HW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_SW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_HW_WRITE_MASK              0x00000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_SW_WRITE_MASK              0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_RSTMASK                    0xc0000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B0_RESET                      0x00000000

// 0x0a70 (BB_PREEMP_COEF_2G_SET0_B0)
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_MASK) >> BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_LSB)
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_LSB) & BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_MASK)
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_Q_0_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_MASK) >> BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_LSB)
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_LSB) & BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_MASK)
#define BB_PREEMP_COEF_2G_SET0_B0_TX_PREEMP_COEF_2G_I_0_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET0_B0_ADDRESS                            0x0a70
#define BB_PREEMP_COEF_2G_SET0_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET0_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET0_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET0_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET0_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET0_B0_RESET                              0x00000000

// 0x0a74 (BB_PREEMP_COEF_2G_SET1_B0)
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_MASK) >> BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_LSB)
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_LSB) & BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_MASK)
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_Q_1_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_MASK) >> BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_LSB)
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_LSB) & BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_MASK)
#define BB_PREEMP_COEF_2G_SET1_B0_TX_PREEMP_COEF_2G_I_1_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET1_B0_ADDRESS                            0x0a74
#define BB_PREEMP_COEF_2G_SET1_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET1_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET1_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET1_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET1_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET1_B0_RESET                              0x00000000

// 0x0a78 (BB_PREEMP_COEF_2G_SET2_B0)
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_MASK) >> BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_LSB)
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_LSB) & BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_MASK)
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_Q_2_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_MASK) >> BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_LSB)
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_LSB) & BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_MASK)
#define BB_PREEMP_COEF_2G_SET2_B0_TX_PREEMP_COEF_2G_I_2_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET2_B0_ADDRESS                            0x0a78
#define BB_PREEMP_COEF_2G_SET2_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET2_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET2_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET2_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET2_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET2_B0_RESET                              0x00000000

// 0x0a7c (BB_PREEMP_COEF_2G_SET3_B0)
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_MASK) >> BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_LSB)
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_LSB) & BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_MASK)
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_Q_3_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_MASK) >> BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_LSB)
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_LSB) & BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_MASK)
#define BB_PREEMP_COEF_2G_SET3_B0_TX_PREEMP_COEF_2G_I_3_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET3_B0_ADDRESS                            0x0a7c
#define BB_PREEMP_COEF_2G_SET3_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET3_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET3_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET3_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET3_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET3_B0_RESET                              0x00000000

// 0x0a80 (BB_PREEMP_COEF_2G_SET4_B0)
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_MASK) >> BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_LSB)
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_LSB) & BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_MASK)
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_Q_4_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_MASK) >> BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_LSB)
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_LSB) & BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_MASK)
#define BB_PREEMP_COEF_2G_SET4_B0_TX_PREEMP_COEF_2G_I_4_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET4_B0_ADDRESS                            0x0a80
#define BB_PREEMP_COEF_2G_SET4_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET4_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET4_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET4_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET4_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET4_B0_RESET                              0x00000000

// 0x0a84 (BB_PREEMP_COEF_2G_SET5_B0)
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_MASK) >> BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_LSB)
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_LSB) & BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_MASK)
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_Q_5_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_MASK) >> BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_LSB)
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_LSB) & BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_MASK)
#define BB_PREEMP_COEF_2G_SET5_B0_TX_PREEMP_COEF_2G_I_5_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET5_B0_ADDRESS                            0x0a84
#define BB_PREEMP_COEF_2G_SET5_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET5_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET5_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET5_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET5_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET5_B0_RESET                              0x00000000

// 0x0a88 (BB_PREEMP_COEF_2G_SET6_B0)
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_MASK) >> BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_LSB)
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_LSB) & BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_MASK)
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_Q_6_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_MASK) >> BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_LSB)
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_LSB) & BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_MASK)
#define BB_PREEMP_COEF_2G_SET6_B0_TX_PREEMP_COEF_2G_I_6_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET6_B0_ADDRESS                            0x0a88
#define BB_PREEMP_COEF_2G_SET6_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET6_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET6_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET6_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET6_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET6_B0_RESET                              0x00000000

// 0x0a8c (BB_PREEMP_COEF_2G_SET7_B0)
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_MASK) >> BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_LSB)
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_LSB) & BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_MASK)
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_Q_7_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_MASK) >> BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_LSB)
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_LSB) & BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_MASK)
#define BB_PREEMP_COEF_2G_SET7_B0_TX_PREEMP_COEF_2G_I_7_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET7_B0_ADDRESS                            0x0a8c
#define BB_PREEMP_COEF_2G_SET7_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET7_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET7_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET7_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET7_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET7_B0_RESET                              0x00000000

// 0x0a90 (BB_PREEMP_COEF_2G_SET8_B0)
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_MSB       23
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_LSB       12
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_MASK) >> BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_LSB)
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_LSB) & BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_MASK)
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_Q_8_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_MSB       11
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_LSB       0
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_MASK) >> BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_LSB)
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_LSB) & BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_MASK)
#define BB_PREEMP_COEF_2G_SET8_B0_TX_PREEMP_COEF_2G_I_8_B0_RESET     0
#define BB_PREEMP_COEF_2G_SET8_B0_ADDRESS                            0x0a90
#define BB_PREEMP_COEF_2G_SET8_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET8_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET8_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET8_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET8_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET8_B0_RESET                              0x00000000

// 0x0a94 (BB_PREEMP_COEF_5G_SET0_B0)
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_MASK) >> BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_LSB)
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_LSB) & BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_MASK)
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_Q_0_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_MASK) >> BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_LSB)
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_LSB) & BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_MASK)
#define BB_PREEMP_COEF_5G_SET0_B0_TX_PREEMP_COEF_5G_I_0_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET0_B0_ADDRESS                            0x0a94
#define BB_PREEMP_COEF_5G_SET0_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET0_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET0_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET0_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET0_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET0_B0_RESET                              0x00000000

// 0x0a98 (BB_PREEMP_COEF_5G_SET1_B0)
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_MASK) >> BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_LSB)
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_LSB) & BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_MASK)
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_Q_1_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_MASK) >> BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_LSB)
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_LSB) & BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_MASK)
#define BB_PREEMP_COEF_5G_SET1_B0_TX_PREEMP_COEF_5G_I_1_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET1_B0_ADDRESS                            0x0a98
#define BB_PREEMP_COEF_5G_SET1_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET1_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET1_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET1_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET1_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET1_B0_RESET                              0x00000000

// 0x0a9c (BB_PREEMP_COEF_5G_SET2_B0)
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_MASK) >> BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_LSB)
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_LSB) & BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_MASK)
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_Q_2_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_MASK) >> BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_LSB)
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_LSB) & BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_MASK)
#define BB_PREEMP_COEF_5G_SET2_B0_TX_PREEMP_COEF_5G_I_2_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET2_B0_ADDRESS                            0x0a9c
#define BB_PREEMP_COEF_5G_SET2_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET2_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET2_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET2_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET2_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET2_B0_RESET                              0x00000000

// 0x0aa0 (BB_PREEMP_COEF_5G_SET3_B0)
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_MASK) >> BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_LSB)
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_LSB) & BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_MASK)
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_Q_3_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_MASK) >> BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_LSB)
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_LSB) & BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_MASK)
#define BB_PREEMP_COEF_5G_SET3_B0_TX_PREEMP_COEF_5G_I_3_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET3_B0_ADDRESS                            0x0aa0
#define BB_PREEMP_COEF_5G_SET3_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET3_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET3_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET3_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET3_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET3_B0_RESET                              0x00000000

// 0x0aa4 (BB_PREEMP_COEF_5G_SET4_B0)
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_MASK) >> BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_LSB)
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_LSB) & BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_MASK)
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_Q_4_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_MASK) >> BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_LSB)
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_LSB) & BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_MASK)
#define BB_PREEMP_COEF_5G_SET4_B0_TX_PREEMP_COEF_5G_I_4_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET4_B0_ADDRESS                            0x0aa4
#define BB_PREEMP_COEF_5G_SET4_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET4_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET4_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET4_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET4_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET4_B0_RESET                              0x00000000

// 0x0aa8 (BB_PREEMP_COEF_5G_SET5_B0)
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_MASK) >> BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_LSB)
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_LSB) & BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_MASK)
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_Q_5_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_MASK) >> BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_LSB)
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_LSB) & BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_MASK)
#define BB_PREEMP_COEF_5G_SET5_B0_TX_PREEMP_COEF_5G_I_5_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET5_B0_ADDRESS                            0x0aa8
#define BB_PREEMP_COEF_5G_SET5_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET5_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET5_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET5_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET5_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET5_B0_RESET                              0x00000000

// 0x0aac (BB_PREEMP_COEF_5G_SET6_B0)
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_MASK) >> BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_LSB)
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_LSB) & BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_MASK)
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_Q_6_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_MASK) >> BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_LSB)
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_LSB) & BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_MASK)
#define BB_PREEMP_COEF_5G_SET6_B0_TX_PREEMP_COEF_5G_I_6_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET6_B0_ADDRESS                            0x0aac
#define BB_PREEMP_COEF_5G_SET6_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET6_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET6_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET6_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET6_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET6_B0_RESET                              0x00000000

// 0x0ab0 (BB_PREEMP_COEF_5G_SET7_B0)
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_MASK) >> BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_LSB)
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_LSB) & BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_MASK)
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_Q_7_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_MASK) >> BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_LSB)
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_LSB) & BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_MASK)
#define BB_PREEMP_COEF_5G_SET7_B0_TX_PREEMP_COEF_5G_I_7_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET7_B0_ADDRESS                            0x0ab0
#define BB_PREEMP_COEF_5G_SET7_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET7_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET7_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET7_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET7_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET7_B0_RESET                              0x00000000

// 0x0ab4 (BB_PREEMP_COEF_5G_SET8_B0)
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_MSB       23
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_LSB       12
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_MASK) >> BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_LSB)
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_LSB) & BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_MASK)
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_Q_8_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_MSB       11
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_LSB       0
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_MASK) >> BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_LSB)
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_LSB) & BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_MASK)
#define BB_PREEMP_COEF_5G_SET8_B0_TX_PREEMP_COEF_5G_I_8_B0_RESET     0
#define BB_PREEMP_COEF_5G_SET8_B0_ADDRESS                            0x0ab4
#define BB_PREEMP_COEF_5G_SET8_B0_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET8_B0_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET8_B0_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET8_B0_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET8_B0_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET8_B0_RESET                              0x00000000

// 0x0ab8 (BB_PREEMP_COEF_CNTLL)
#define BB_PREEMP_COEF_CNTLL_PREEMP_MASK_MSB                         31
#define BB_PREEMP_COEF_CNTLL_PREEMP_MASK_LSB                         1
#define BB_PREEMP_COEF_CNTLL_PREEMP_MASK_MASK                        0xfffffffe
#define BB_PREEMP_COEF_CNTLL_PREEMP_MASK_GET(x)                      (((x) & BB_PREEMP_COEF_CNTLL_PREEMP_MASK_MASK) >> BB_PREEMP_COEF_CNTLL_PREEMP_MASK_LSB)
#define BB_PREEMP_COEF_CNTLL_PREEMP_MASK_SET(x)                      (((0 | (x)) << BB_PREEMP_COEF_CNTLL_PREEMP_MASK_LSB) & BB_PREEMP_COEF_CNTLL_PREEMP_MASK_MASK)
#define BB_PREEMP_COEF_CNTLL_PREEMP_MASK_RESET                       2147483647
#define BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_MSB                    0
#define BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_LSB                    0
#define BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_MASK                   0x00000001
#define BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_GET(x)                 (((x) & BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_MASK) >> BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_LSB)
#define BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_SET(x)                 (((0 | (x)) << BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_LSB) & BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_MASK)
#define BB_PREEMP_COEF_CNTLL_TX_PREEMP_FIR_EN_RESET                  0
#define BB_PREEMP_COEF_CNTLL_ADDRESS                                 0x0ab8
#define BB_PREEMP_COEF_CNTLL_HW_MASK                                 0xffffffff
#define BB_PREEMP_COEF_CNTLL_SW_MASK                                 0xffffffff
#define BB_PREEMP_COEF_CNTLL_HW_WRITE_MASK                           0x00000000
#define BB_PREEMP_COEF_CNTLL_SW_WRITE_MASK                           0xffffffff
#define BB_PREEMP_COEF_CNTLL_RSTMASK                                 0xffffffff
#define BB_PREEMP_COEF_CNTLL_RESET                                   0xfffffffe

// 0x0b00 (BB_TX_PLYBCK_CTRL_0_B0)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_MSB                31
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_LSB                16
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_MASK               0xffff0000
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_GET(x)             (((x) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_MASK) >> BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_LSB)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_SET(x)             (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_LSB) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_MASK)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_NSAMPLES_RESET              0
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_MSB              15
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_LSB              8
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_MASK             0x0000ff00
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_GET(x)           (((x) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_MASK) >> BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_LSB)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_SET(x)           (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_LSB) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_MASK)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_START_ADDR_RESET            0
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_MSB                 3
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_LSB                 2
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_MASK                0x0000000c
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_GET(x)              (((x) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_MASK) >> BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_LSB)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_SET(x)              (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_LSB) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_MASK)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_RD_MODE_RESET               0
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_MSB                   1
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_LSB                   1
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_MASK                  0x00000002
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_GET(x)                (((x) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_MASK) >> BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_LSB)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_SET(x)                (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_LSB) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_MASK)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_SW_WE_RESET                 0
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_MSB                  0
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_LSB                  0
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_MASK                 0x00000001
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_GET(x)               (((x) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_MASK) >> BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_LSB)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_SET(x)               (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_LSB) & BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_MASK)
#define BB_TX_PLYBCK_CTRL_0_B0_TX_PLYBCK_ENABLE_RESET                0
#define BB_TX_PLYBCK_CTRL_0_B0_ADDRESS                               0x0b00
#define BB_TX_PLYBCK_CTRL_0_B0_HW_MASK                               0xffffff0f
#define BB_TX_PLYBCK_CTRL_0_B0_SW_MASK                               0xffffff0f
#define BB_TX_PLYBCK_CTRL_0_B0_HW_WRITE_MASK                         0x00000000
#define BB_TX_PLYBCK_CTRL_0_B0_SW_WRITE_MASK                         0xffffff0f
#define BB_TX_PLYBCK_CTRL_0_B0_RSTMASK                               0x000000f1
#define BB_TX_PLYBCK_CTRL_0_B0_RESET                                 0x00000000

// 0x0c00 (BB_NORMRX_RXIQ_CORR_COEFF_B0_0)
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_MSB 17
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_LSB 0
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_MASK 0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_GET(x) (((x) & BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_MASK) >> BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_LSB)
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_SET(x) (((0 | (x)) << BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_LSB) & BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_MASK)
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_NORMRX_IQC_COEFF_TABLE_CHN0_RESET 0
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_ADDRESS                       0x0c00
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_ADDRESS                         BB_NORMRX_RXIQ_CORR_COEFF_B0_0_ADDRESS
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_HW_MASK                       0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_SW_MASK                       0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_HW_WRITE_MASK                 0x00000000
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_SW_WRITE_MASK                 0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_RSTMASK                       0xffffffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B0_0_RESET                         0x00000000

// Skip c04 (BB_NORMRX_RXIQ_CORR_COEFF_B0_1) - e7c (BB_NORMRX_RXIQ_CORR_COEFF_B0_159) for brevity
// 0x0e80 (BB_PAPRD_MEM_TAB_B0_0)
#define BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_MSB                          21
#define BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_LSB                          0
#define BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_MASK                         0x003fffff
#define BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_GET(x)                       (((x) & BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_MASK) >> BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_LSB)
#define BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_SET(x)                       (((0 | (x)) << BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_LSB) & BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_MASK)
#define BB_PAPRD_MEM_TAB_B0_0_PAPRD_MEM_RESET                        0
#define BB_PAPRD_MEM_TAB_B0_0_ADDRESS                                0x0e80
#define BB_PAPRD_MEM_TAB_B0_ADDRESS                                  BB_PAPRD_MEM_TAB_B0_0_ADDRESS
#define BB_PAPRD_MEM_TAB_B0_0_HW_MASK                                0x003fffff
#define BB_PAPRD_MEM_TAB_B0_0_SW_MASK                                0x003fffff
#define BB_PAPRD_MEM_TAB_B0_0_HW_WRITE_MASK                          0x00000000
#define BB_PAPRD_MEM_TAB_B0_0_SW_WRITE_MASK                          0x003fffff
#define BB_PAPRD_MEM_TAB_B0_0_RSTMASK                                0xffc00000
#define BB_PAPRD_MEM_TAB_B0_0_RESET                                  0x00000000

// Skip e84 (BB_PAPRD_MEM_TAB_B0_1) - 1a7c (BB_PAPRD_MEM_TAB_B0_767) for brevity
// 0x2400 (BB_PAPRD_TRAINER_CNTL1)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_MSB               31
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_LSB               31
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_MASK              0x80000000
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_GET(x)            (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_SET(x)            (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_MODE_RESET             0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_MSB          26
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_LSB          25
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_MASK         0x06000000
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_GET(x)       (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_SET(x)       (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_FINE_IDX_RESET        0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_MSB        24
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_LSB        20
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_MASK       0x01f00000
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_GET(x)     (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_SET(x)     (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_FORCED_COARSE_IDX_RESET      0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_MSB               19
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_LSB               19
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_MASK              0x00080000
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_GET(x)            (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_SET(x)            (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_CORR_FORCE_RESET             0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_MSB           11
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_LSB           11
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_MASK          0x00000800
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_GET(x)        (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_SET(x)        (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_DC_CORR_ENABLE_RESET         1
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB            10
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB            10
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK           0x00000400
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x)         (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x)         (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_RESET          0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB         9
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB         9
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK        0x00000200
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x)      (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x)      (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_RESET       0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB            8
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB            8
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK           0x00000100
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x)         (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x)         (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_RESET          0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB            7
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB            1
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK           0x000000fe
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x)         (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x)         (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_RESET          28
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB             0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB             0
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK            0x00000001
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x)          (((x) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK) >> BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x)          (((0 | (x)) << BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB) & BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK)
#define BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_RESET           0
#define BB_PAPRD_TRAINER_CNTL1_ADDRESS                               0x2400
#define BB_PAPRD_TRAINER_CNTL1_HW_MASK                               0x87f80fff
#define BB_PAPRD_TRAINER_CNTL1_SW_MASK                               0x87f80fff
#define BB_PAPRD_TRAINER_CNTL1_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_TRAINER_CNTL1_SW_WRITE_MASK                         0x87f80fff
#define BB_PAPRD_TRAINER_CNTL1_RSTMASK                               0xffffffff
#define BB_PAPRD_TRAINER_CNTL1_RESET                                 0x00000838

// 0x2404 (BB_PAPRD_TRAINER_CNTL2)
#define BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB          31
#define BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB          0
#define BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK         0xffffffff
#define BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x)       (((x) & BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK) >> BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB)
#define BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x)       (((0 | (x)) << BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB) & BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK)
#define BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_RESET        137
#define BB_PAPRD_TRAINER_CNTL2_ADDRESS                               0x2404
#define BB_PAPRD_TRAINER_CNTL2_HW_MASK                               0xffffffff
#define BB_PAPRD_TRAINER_CNTL2_SW_MASK                               0xffffffff
#define BB_PAPRD_TRAINER_CNTL2_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_TRAINER_CNTL2_SW_WRITE_MASK                         0xffffffff
#define BB_PAPRD_TRAINER_CNTL2_RSTMASK                               0xffffffff
#define BB_PAPRD_TRAINER_CNTL2_RESET                                 0x00000089

// 0x2408 (BB_PAPRD_TRAINER_CNTL3)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB          29
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB          29
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK         0x20000000
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x)       (((x) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK) >> BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x)       (((0 | (x)) << BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_RESET        0
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB            27
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB            24
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK           0x0f000000
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x)         (((x) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK) >> BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x)         (((0 | (x)) << BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_RESET          2
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB          23
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB          20
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK         0x00f00000
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x)       (((x) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK) >> BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x)       (((0 | (x)) << BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_RESET        2
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB          19
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB          17
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK         0x000e0000
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x)       (((x) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK) >> BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x)       (((0 | (x)) << BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_RESET        7
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB         16
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB         12
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK        0x0001f000
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x)      (((x) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK) >> BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x)      (((0 | (x)) << BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_RESET       03
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB               11
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB               6
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK              0x00000fc0
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x)            (((x) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK) >> BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x)            (((0 | (x)) << BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB) & BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK)
#define BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_RESET             61
#define BB_PAPRD_TRAINER_CNTL3_ADDRESS                               0x2408
#define BB_PAPRD_TRAINER_CNTL3_HW_MASK                               0x2fffffc0
#define BB_PAPRD_TRAINER_CNTL3_SW_MASK                               0x2fffffc0
#define BB_PAPRD_TRAINER_CNTL3_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_TRAINER_CNTL3_SW_WRITE_MASK                         0x2fffffc0
#define BB_PAPRD_TRAINER_CNTL3_RSTMASK                               0xffffffff
#define BB_PAPRD_TRAINER_CNTL3_RESET                                 0x022e3f40

// 0x240c (BB_PAPRD_TRAINER_CNTL4)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB        25
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB        16
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK       0x03ff0000
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x)     (((x) & BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK) >> BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x)     (((0 | (x)) << BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB) & BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_RESET      64
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB             15
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB             12
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK            0x0000f000
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x)          (((x) & BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK) >> BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x)          (((0 | (x)) << BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB) & BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_RESET           0
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB                 11
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB                 0
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK                0x00000fff
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x)              (((x) & BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK) >> BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x)              (((0 | (x)) << BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB) & BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK)
#define BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_RESET               400
#define BB_PAPRD_TRAINER_CNTL4_ADDRESS                               0x240c
#define BB_PAPRD_TRAINER_CNTL4_HW_MASK                               0x03ffffff
#define BB_PAPRD_TRAINER_CNTL4_SW_MASK                               0x03ffffff
#define BB_PAPRD_TRAINER_CNTL4_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_TRAINER_CNTL4_SW_WRITE_MASK                         0x03ffffff
#define BB_PAPRD_TRAINER_CNTL4_RSTMASK                               0xffffffff
#define BB_PAPRD_TRAINER_CNTL4_RESET                                 0x00400190

// 0x2410 (BB_PAPRD_TRAINER_STAT1)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_MSB                  17
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_LSB                  17
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_MASK                 0x00020000
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_GET(x)               (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_SET(x)               (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_SIZED_RESET                0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB                    16
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB                    9
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK                   0x0001fe00
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x)                 (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_SET(x)                 (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_RESET                  0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB                 8
#define BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB                 4
#define BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK                0x000001f0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x)              (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_SET(x)              (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_RESET               0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB                3
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB                3
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK               0x00000008
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x)             (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_SET(x)             (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_RESET              0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB                    2
#define BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB                    2
#define BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK                   0x00000004
#define BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x)                 (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_SET(x)                 (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_RESET                  0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB            1
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB            1
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK           0x00000002
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x)         (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_SET(x)         (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_RESET          0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB                  0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB                  0
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK                 0x00000001
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x)               (((x) & BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK) >> BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x)               (((0 | (x)) << BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB) & BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK)
#define BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_RESET                0
#define BB_PAPRD_TRAINER_STAT1_ADDRESS                               0x2410
#define BB_PAPRD_TRAINER_STAT1_HW_MASK                               0x0003ffff
#define BB_PAPRD_TRAINER_STAT1_SW_MASK                               0x0003ffff
#define BB_PAPRD_TRAINER_STAT1_HW_WRITE_MASK                         0x0003fffe
#define BB_PAPRD_TRAINER_STAT1_SW_WRITE_MASK                         0x00000001
#define BB_PAPRD_TRAINER_STAT1_RSTMASK                               0xfffc0001
#define BB_PAPRD_TRAINER_STAT1_RESET                                 0x00000000

// 0x2414 (BB_PAPRD_TRAINER_STAT2)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB                    22
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB                    21
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK                   0x00600000
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x)                 (((x) & BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK) >> BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_SET(x)                 (((0 | (x)) << BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB) & BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_RESET                  0
#define BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB                  20
#define BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB                  16
#define BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK                 0x001f0000
#define BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x)               (((x) & BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK) >> BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_SET(x)               (((0 | (x)) << BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB) & BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_RESET                0
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB                    15
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB                    0
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK                   0x0000ffff
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x)                 (((x) & BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK) >> BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_SET(x)                 (((0 | (x)) << BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB) & BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK)
#define BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_RESET                  0
#define BB_PAPRD_TRAINER_STAT2_ADDRESS                               0x2414
#define BB_PAPRD_TRAINER_STAT2_HW_MASK                               0x007fffff
#define BB_PAPRD_TRAINER_STAT2_SW_MASK                               0x007fffff
#define BB_PAPRD_TRAINER_STAT2_HW_WRITE_MASK                         0x007fffff
#define BB_PAPRD_TRAINER_STAT2_SW_WRITE_MASK                         0x00000000
#define BB_PAPRD_TRAINER_STAT2_RSTMASK                               0xffffffff
#define BB_PAPRD_TRAINER_STAT2_RESET                                 0x00000000

// 0x2418 (BB_PAPRD_TRAINER_STAT3)
#define BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB           19
#define BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB           0
#define BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK          0x000fffff
#define BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x)        (((x) & BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK) >> BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB)
#define BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_SET(x)        (((0 | (x)) << BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB) & BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK)
#define BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_RESET         0
#define BB_PAPRD_TRAINER_STAT3_ADDRESS                               0x2418
#define BB_PAPRD_TRAINER_STAT3_HW_MASK                               0x000fffff
#define BB_PAPRD_TRAINER_STAT3_SW_MASK                               0x000fffff
#define BB_PAPRD_TRAINER_STAT3_HW_WRITE_MASK                         0x000fffff
#define BB_PAPRD_TRAINER_STAT3_SW_WRITE_MASK                         0x00000000
#define BB_PAPRD_TRAINER_STAT3_RSTMASK                               0xffffffff
#define BB_PAPRD_TRAINER_STAT3_RESET                                 0x00000000

// 0x241c (BB_PAPRD_TRAIN_GAIN_SET0)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_MSB                26
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_LSB                18
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_MASK               0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_MASK) >> BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_LSB) & BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_2_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_MSB                17
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_LSB                9
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_MASK               0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_MASK) >> BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_LSB) & BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_1_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_MSB                8
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_LSB                0
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_MASK               0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_MASK) >> BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_LSB) & BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET0_PAPRD_GAIN_TBL_0_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET0_ADDRESS                             0x241c
#define BB_PAPRD_TRAIN_GAIN_SET0_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET0_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET0_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET0_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET0_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET0_RESET                               0x00000000

// 0x2420 (BB_PAPRD_TRAIN_GAIN_SET1)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_MSB                26
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_LSB                18
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_MASK               0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_MASK) >> BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_LSB) & BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_5_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_MSB                17
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_LSB                9
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_MASK               0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_MASK) >> BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_LSB) & BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_4_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_MSB                8
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_LSB                0
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_MASK               0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_MASK) >> BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_LSB) & BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET1_PAPRD_GAIN_TBL_3_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET1_ADDRESS                             0x2420
#define BB_PAPRD_TRAIN_GAIN_SET1_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET1_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET1_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET1_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET1_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET1_RESET                               0x00000000

// 0x2424 (BB_PAPRD_TRAIN_GAIN_SET2)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_MSB                26
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_LSB                18
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_MASK               0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_MASK) >> BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_LSB) & BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_8_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_MSB                17
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_LSB                9
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_MASK               0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_MASK) >> BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_LSB) & BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_7_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_MSB                8
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_LSB                0
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_MASK               0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_MASK) >> BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_LSB) & BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET2_PAPRD_GAIN_TBL_6_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET2_ADDRESS                             0x2424
#define BB_PAPRD_TRAIN_GAIN_SET2_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET2_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET2_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET2_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET2_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET2_RESET                               0x00000000

// 0x2428 (BB_PAPRD_TRAIN_GAIN_SET3)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_MSB               26
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_LSB               18
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_MASK              0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_MASK) >> BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_LSB) & BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_11_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_MSB               17
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_LSB               9
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_MASK              0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_MASK) >> BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_LSB) & BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_10_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_MSB                8
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_LSB                0
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_MASK               0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_GET(x)             (((x) & BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_MASK) >> BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_SET(x)             (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_LSB) & BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET3_PAPRD_GAIN_TBL_9_RESET              0
#define BB_PAPRD_TRAIN_GAIN_SET3_ADDRESS                             0x2428
#define BB_PAPRD_TRAIN_GAIN_SET3_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET3_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET3_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET3_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET3_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET3_RESET                               0x00000000

// 0x242c (BB_PAPRD_TRAIN_GAIN_SET4)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_MSB               26
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_LSB               18
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_MASK              0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_MASK) >> BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_LSB) & BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_14_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_MSB               17
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_LSB               9
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_MASK              0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_MASK) >> BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_LSB) & BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_13_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_MSB               8
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_LSB               0
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_MASK              0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_MASK) >> BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_LSB) & BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET4_PAPRD_GAIN_TBL_12_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET4_ADDRESS                             0x242c
#define BB_PAPRD_TRAIN_GAIN_SET4_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET4_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET4_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET4_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET4_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET4_RESET                               0x00000000

// 0x2430 (BB_PAPRD_TRAIN_GAIN_SET5)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_MSB               26
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_LSB               18
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_MASK              0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_MASK) >> BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_LSB) & BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_17_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_MSB               17
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_LSB               9
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_MASK              0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_MASK) >> BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_LSB) & BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_16_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_MSB               8
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_LSB               0
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_MASK              0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_MASK) >> BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_LSB) & BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET5_PAPRD_GAIN_TBL_15_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET5_ADDRESS                             0x2430
#define BB_PAPRD_TRAIN_GAIN_SET5_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET5_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET5_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET5_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET5_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET5_RESET                               0x00000000

// 0x2434 (BB_PAPRD_TRAIN_GAIN_SET6)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_MSB               26
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_LSB               18
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_MASK              0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_MASK) >> BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_LSB) & BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_20_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_MSB               17
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_LSB               9
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_MASK              0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_MASK) >> BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_LSB) & BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_19_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_MSB               8
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_LSB               0
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_MASK              0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_MASK) >> BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_LSB) & BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET6_PAPRD_GAIN_TBL_18_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET6_ADDRESS                             0x2434
#define BB_PAPRD_TRAIN_GAIN_SET6_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET6_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET6_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET6_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET6_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET6_RESET                               0x00000000

// 0x2438 (BB_PAPRD_TRAIN_GAIN_SET7)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_MSB               26
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_LSB               18
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_MASK              0x07fc0000
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_MASK) >> BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_LSB) & BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_23_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_MSB               17
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_LSB               9
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_MASK              0x0003fe00
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_MASK) >> BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_LSB) & BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_22_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_MSB               8
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_LSB               0
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_MASK              0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_MASK) >> BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_LSB) & BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET7_PAPRD_GAIN_TBL_21_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET7_ADDRESS                             0x2438
#define BB_PAPRD_TRAIN_GAIN_SET7_HW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET7_SW_MASK                             0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET7_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET7_SW_WRITE_MASK                       0x07ffffff
#define BB_PAPRD_TRAIN_GAIN_SET7_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET7_RESET                               0x00000000

// 0x243c (BB_PAPRD_TRAIN_GAIN_SET8)
#define BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_MSB               8
#define BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_LSB               0
#define BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_MASK              0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_GET(x)            (((x) & BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_MASK) >> BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_LSB)
#define BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_LSB) & BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_MASK)
#define BB_PAPRD_TRAIN_GAIN_SET8_PAPRD_GAIN_TBL_24_RESET             0
#define BB_PAPRD_TRAIN_GAIN_SET8_ADDRESS                             0x243c
#define BB_PAPRD_TRAIN_GAIN_SET8_HW_MASK                             0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET8_SW_MASK                             0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET8_HW_WRITE_MASK                       0x00000000
#define BB_PAPRD_TRAIN_GAIN_SET8_SW_WRITE_MASK                       0x000001ff
#define BB_PAPRD_TRAIN_GAIN_SET8_RSTMASK                             0xffffffff
#define BB_PAPRD_TRAIN_GAIN_SET8_RESET                               0x00000000

// 0x2440 (BB_PAPRD_TRAIN_GAIN_IDX_SET0)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_MSB            31
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_LSB            0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_MASK           0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_GET(x)         (((x) & BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_MASK) >> BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_LSB)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_SET(x)         (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_LSB) & BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_MASK)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_PAPRD_GAIN_IDX_0_RESET          0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_ADDRESS                         0x2440
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_HW_MASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_SW_MASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_HW_WRITE_MASK                   0x00000000
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_SW_WRITE_MASK                   0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_RSTMASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET0_RESET                           0x00000000

// 0x2444 (BB_PAPRD_TRAIN_GAIN_IDX_SET1)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_MSB            31
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_LSB            0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_MASK           0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_GET(x)         (((x) & BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_MASK) >> BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_LSB)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_SET(x)         (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_LSB) & BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_MASK)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_PAPRD_GAIN_IDX_1_RESET          0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_ADDRESS                         0x2444
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_HW_MASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_SW_MASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_HW_WRITE_MASK                   0x00000000
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_SW_WRITE_MASK                   0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_RSTMASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET1_RESET                           0x00000000

// 0x2448 (BB_PAPRD_TRAIN_GAIN_IDX_SET2)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_MSB            31
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_LSB            0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_MASK           0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_GET(x)         (((x) & BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_MASK) >> BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_LSB)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_SET(x)         (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_LSB) & BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_MASK)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_PAPRD_GAIN_IDX_2_RESET          0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_ADDRESS                         0x2448
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_HW_MASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_SW_MASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_HW_WRITE_MASK                   0x00000000
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_SW_WRITE_MASK                   0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_RSTMASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET2_RESET                           0x00000000

// 0x244c (BB_PAPRD_TRAIN_GAIN_IDX_SET3)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_MSB            3
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_LSB            0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_MASK           0x0000000f
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_GET(x)         (((x) & BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_MASK) >> BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_LSB)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_SET(x)         (((0 | (x)) << BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_LSB) & BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_MASK)
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_PAPRD_GAIN_IDX_3_RESET          0
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_ADDRESS                         0x244c
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_HW_MASK                         0x0000000f
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_SW_MASK                         0x0000000f
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_HW_WRITE_MASK                   0x00000000
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_SW_WRITE_MASK                   0x0000000f
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_RSTMASK                         0xffffffff
#define BB_PAPRD_TRAIN_GAIN_IDX_SET3_RESET                           0x00000000

// 0x2450 (BB_PAPRD_TRAIN_AGC0)
#define BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_MSB                   29
#define BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_LSB                   26
#define BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_MASK                  0x3c000000
#define BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_GET(x)                (((x) & BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_MASK) >> BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_LSB)
#define BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_SET(x)                (((0 | (x)) << BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_LSB) & BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_MASK)
#define BB_PAPRD_TRAIN_AGC0_CONSEC_GAIN_CHANGE_RESET                 0
#define BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_MSB                   25
#define BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_LSB                   24
#define BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_MASK                  0x03000000
#define BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_GET(x)                (((x) & BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_MASK) >> BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_LSB)
#define BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_SET(x)                (((0 | (x)) << BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_LSB) & BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_MASK)
#define BB_PAPRD_TRAIN_AGC0_CONSEC_PWR_LOW_CNT_RESET                 0
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_MSB                       23
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_LSB                       16
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_MASK                      0x00ff0000
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_GET(x)                    (((x) & BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_MASK) >> BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_LSB)
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_SET(x)                    (((0 | (x)) << BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_LSB) & BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_MASK)
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_WEAK_RESET                     0
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_MSB                        15
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_LSB                        8
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_MASK                       0x0000ff00
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_GET(x)                     (((x) & BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_MASK) >> BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_LSB)
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_SET(x)                     (((0 | (x)) << BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_LSB) & BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_MASK)
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_LOW_RESET                      0
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_MSB                       7
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_LSB                       0
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_MASK                      0x000000ff
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_GET(x)                    (((x) & BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_MASK) >> BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_LSB)
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_SET(x)                    (((0 | (x)) << BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_LSB) & BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_MASK)
#define BB_PAPRD_TRAIN_AGC0_PAPRD_PWR_HIGH_RESET                     0
#define BB_PAPRD_TRAIN_AGC0_ADDRESS                                  0x2450
#define BB_PAPRD_TRAIN_AGC0_HW_MASK                                  0x3fffffff
#define BB_PAPRD_TRAIN_AGC0_SW_MASK                                  0x3fffffff
#define BB_PAPRD_TRAIN_AGC0_HW_WRITE_MASK                            0x00000000
#define BB_PAPRD_TRAIN_AGC0_SW_WRITE_MASK                            0x3fffffff
#define BB_PAPRD_TRAIN_AGC0_RSTMASK                                  0xffffffff
#define BB_PAPRD_TRAIN_AGC0_RESET                                    0x00000000

// 0x2454 (BB_PAPRD_TRAIN_AGC1)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_MSB                   17
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_LSB                   12
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_MASK                  0x0003f000
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_GET(x)                (((x) & BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_MASK) >> BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_LSB)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_SET(x)                (((0 | (x)) << BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_LSB) & BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_MASK)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_WEAK_DB_RESET                 0
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_MSB                    11
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_LSB                    6
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_MASK                   0x00000fc0
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_GET(x)                 (((x) & BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_MASK) >> BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_LSB)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_SET(x)                 (((0 | (x)) << BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_LSB) & BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_MASK)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_LOW_DB_RESET                  0
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_MSB                     5
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_LSB                     0
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_MASK                    0x0000003f
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_GET(x)                  (((x) & BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_MASK) >> BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_LSB)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_SET(x)                  (((0 | (x)) << BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_LSB) & BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_MASK)
#define BB_PAPRD_TRAIN_AGC1_TARGET_LVL_HI_DB_RESET                   0
#define BB_PAPRD_TRAIN_AGC1_ADDRESS                                  0x2454
#define BB_PAPRD_TRAIN_AGC1_HW_MASK                                  0x0003ffff
#define BB_PAPRD_TRAIN_AGC1_SW_MASK                                  0x0003ffff
#define BB_PAPRD_TRAIN_AGC1_HW_WRITE_MASK                            0x00000000
#define BB_PAPRD_TRAIN_AGC1_SW_WRITE_MASK                            0x0003ffff
#define BB_PAPRD_TRAIN_AGC1_RSTMASK                                  0xffffffff
#define BB_PAPRD_TRAIN_AGC1_RESET                                    0x00000000

// 0x2458 (BB_PAPRD_TRAIN_QCHK_ACC_0)
#define BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_MSB               23
#define BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_LSB               0
#define BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_MASK              0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_GET(x)            (((x) & BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_MASK) >> BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_LSB)
#define BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_LSB) & BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_MASK)
#define BB_PAPRD_TRAIN_QCHK_ACC_0_PAPRD_QCHK_ACC_0_RESET             0
#define BB_PAPRD_TRAIN_QCHK_ACC_0_ADDRESS                            0x2458
#define BB_PAPRD_TRAIN_QCHK_ACC_0_HW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_0_SW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_0_HW_WRITE_MASK                      0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_0_SW_WRITE_MASK                      0x00000000
#define BB_PAPRD_TRAIN_QCHK_ACC_0_RSTMASK                            0xff000000
#define BB_PAPRD_TRAIN_QCHK_ACC_0_RESET                              0x00000000

// 0x245c (BB_PAPRD_TRAIN_QCHK_ACC_1)
#define BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_MSB               23
#define BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_LSB               0
#define BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_MASK              0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_GET(x)            (((x) & BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_MASK) >> BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_LSB)
#define BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_LSB) & BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_MASK)
#define BB_PAPRD_TRAIN_QCHK_ACC_1_PAPRD_QCHK_ACC_1_RESET             0
#define BB_PAPRD_TRAIN_QCHK_ACC_1_ADDRESS                            0x245c
#define BB_PAPRD_TRAIN_QCHK_ACC_1_HW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_1_SW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_1_HW_WRITE_MASK                      0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_1_SW_WRITE_MASK                      0x00000000
#define BB_PAPRD_TRAIN_QCHK_ACC_1_RSTMASK                            0xff000000
#define BB_PAPRD_TRAIN_QCHK_ACC_1_RESET                              0x00000000

// 0x2460 (BB_PAPRD_TRAIN_QCHK_ACC_2)
#define BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_MSB               23
#define BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_LSB               0
#define BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_MASK              0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_GET(x)            (((x) & BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_MASK) >> BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_LSB)
#define BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_LSB) & BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_MASK)
#define BB_PAPRD_TRAIN_QCHK_ACC_2_PAPRD_QCHK_ACC_2_RESET             0
#define BB_PAPRD_TRAIN_QCHK_ACC_2_ADDRESS                            0x2460
#define BB_PAPRD_TRAIN_QCHK_ACC_2_HW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_2_SW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_2_HW_WRITE_MASK                      0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_2_SW_WRITE_MASK                      0x00000000
#define BB_PAPRD_TRAIN_QCHK_ACC_2_RSTMASK                            0xff000000
#define BB_PAPRD_TRAIN_QCHK_ACC_2_RESET                              0x00000000

// 0x2464 (BB_PAPRD_TRAIN_QCHK_ACC_3)
#define BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_MSB               23
#define BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_LSB               0
#define BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_MASK              0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_GET(x)            (((x) & BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_MASK) >> BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_LSB)
#define BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_SET(x)            (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_LSB) & BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_MASK)
#define BB_PAPRD_TRAIN_QCHK_ACC_3_PAPRD_QCHK_ACC_3_RESET             0
#define BB_PAPRD_TRAIN_QCHK_ACC_3_ADDRESS                            0x2464
#define BB_PAPRD_TRAIN_QCHK_ACC_3_HW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_3_SW_MASK                            0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_3_HW_WRITE_MASK                      0x00ffffff
#define BB_PAPRD_TRAIN_QCHK_ACC_3_SW_WRITE_MASK                      0x00000000
#define BB_PAPRD_TRAIN_QCHK_ACC_3_RSTMASK                            0xff000000
#define BB_PAPRD_TRAIN_QCHK_ACC_3_RESET                              0x00000000

// 0x2468 (BB_PAPRD_TRAIN_QCHK_DATA_0)
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_MSB              21
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_LSB              11
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_MASK             0x003ff800
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MAX_0_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_MSB              10
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_LSB              0
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_MASK             0x000007ff
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_0_PAPRD_QCHK_MIN_0_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_0_ADDRESS                           0x2468
#define BB_PAPRD_TRAIN_QCHK_DATA_0_HW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_0_SW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_0_HW_WRITE_MASK                     0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_0_SW_WRITE_MASK                     0x00000000
#define BB_PAPRD_TRAIN_QCHK_DATA_0_RSTMASK                           0xffc00000
#define BB_PAPRD_TRAIN_QCHK_DATA_0_RESET                             0x00000000

// 0x246c (BB_PAPRD_TRAIN_QCHK_DATA_1)
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_MSB              21
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_LSB              11
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_MASK             0x003ff800
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MAX_1_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_MSB              10
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_LSB              0
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_MASK             0x000007ff
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_1_PAPRD_QCHK_MIN_1_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_1_ADDRESS                           0x246c
#define BB_PAPRD_TRAIN_QCHK_DATA_1_HW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_1_SW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_1_HW_WRITE_MASK                     0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_1_SW_WRITE_MASK                     0x00000000
#define BB_PAPRD_TRAIN_QCHK_DATA_1_RSTMASK                           0xffc00000
#define BB_PAPRD_TRAIN_QCHK_DATA_1_RESET                             0x00000000

// 0x2470 (BB_PAPRD_TRAIN_QCHK_DATA_2)
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_MSB              21
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_LSB              11
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_MASK             0x003ff800
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MAX_2_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_MSB              10
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_LSB              0
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_MASK             0x000007ff
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_2_PAPRD_QCHK_MIN_2_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_2_ADDRESS                           0x2470
#define BB_PAPRD_TRAIN_QCHK_DATA_2_HW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_2_SW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_2_HW_WRITE_MASK                     0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_2_SW_WRITE_MASK                     0x00000000
#define BB_PAPRD_TRAIN_QCHK_DATA_2_RSTMASK                           0xffc00000
#define BB_PAPRD_TRAIN_QCHK_DATA_2_RESET                             0x00000000

// 0x2474 (BB_PAPRD_TRAIN_QCHK_DATA_3)
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_MSB              21
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_LSB              11
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_MASK             0x003ff800
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MAX_3_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_MSB              10
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_LSB              0
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_MASK             0x000007ff
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_GET(x)           (((x) & BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_MASK) >> BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_LSB)
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_SET(x)           (((0 | (x)) << BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_LSB) & BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_MASK)
#define BB_PAPRD_TRAIN_QCHK_DATA_3_PAPRD_QCHK_MIN_3_RESET            0
#define BB_PAPRD_TRAIN_QCHK_DATA_3_ADDRESS                           0x2474
#define BB_PAPRD_TRAIN_QCHK_DATA_3_HW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_3_SW_MASK                           0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_3_HW_WRITE_MASK                     0x003fffff
#define BB_PAPRD_TRAIN_QCHK_DATA_3_SW_WRITE_MASK                     0x00000000
#define BB_PAPRD_TRAIN_QCHK_DATA_3_RSTMASK                           0xffc00000
#define BB_PAPRD_TRAIN_QCHK_DATA_3_RESET                             0x00000000

// 0x2478 (BB_PAPRD_TRAIN_MEM_0)
#define BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_MSB                      31
#define BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_LSB                      0
#define BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_MASK                     0xffffffff
#define BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_GET(x)                   (((x) & BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_MASK) >> BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_LSB)
#define BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_SET(x)                   (((0 | (x)) << BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_LSB) & BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_MASK)
#define BB_PAPRD_TRAIN_MEM_0_PAPRD_TRN_DATA_RESET                    0
#define BB_PAPRD_TRAIN_MEM_0_ADDRESS                                 0x2478
#define BB_PAPRD_TRAIN_MEM_ADDRESS                                   BB_PAPRD_TRAIN_MEM_0_ADDRESS
#define BB_PAPRD_TRAIN_MEM_0_HW_MASK                                 0xffffffff
#define BB_PAPRD_TRAIN_MEM_0_SW_MASK                                 0xffffffff
#define BB_PAPRD_TRAIN_MEM_0_HW_WRITE_MASK                           0xffffffff
#define BB_PAPRD_TRAIN_MEM_0_SW_WRITE_MASK                           0x00000000
#define BB_PAPRD_TRAIN_MEM_0_RSTMASK                                 0x00000000
#define BB_PAPRD_TRAIN_MEM_0_RESET                                   0x00000000

// Skip 247c (BB_PAPRD_TRAIN_MEM_1) - 2a74 (BB_PAPRD_TRAIN_MEM_383) for brevity
// 0x2ee0 (BB_NORMTX_TXIQ_CORR_COEFF_B0_0)
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_MSB 17
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_LSB 0
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_MASK 0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_GET(x) (((x) & BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_MASK) >> BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_LSB)
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_SET(x) (((0 | (x)) << BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_LSB) & BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_MASK)
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_NORMTX_IQC_COEFF_TABLE_CHN0_RESET 0
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_ADDRESS                       0x2ee0
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_ADDRESS                         BB_NORMTX_TXIQ_CORR_COEFF_B0_0_ADDRESS
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_HW_MASK                       0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_SW_MASK                       0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_HW_WRITE_MASK                 0x00000000
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_SW_WRITE_MASK                 0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_RSTMASK                       0xffffffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B0_0_RESET                         0x00000000

// Skip 2ee4 (BB_NORMTX_TXIQ_CORR_COEFF_B0_1) - 315c (BB_NORMTX_TXIQ_CORR_COEFF_B0_159) for brevity
// 0x3200 (BB_CHANINFO_TAB_B0_0)
#define BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_MSB                       31
#define BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_LSB                       0
#define BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_MASK                      0xffffffff
#define BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_GET(x)                    (((x) & BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_MASK) >> BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_LSB)
#define BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_SET(x)                    (((0 | (x)) << BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_LSB) & BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_MASK)
#define BB_CHANINFO_TAB_B0_0_CHANINFO_WORD_RESET                     0
#define BB_CHANINFO_TAB_B0_0_ADDRESS                                 0x3200
#define BB_CHANINFO_TAB_B0_ADDRESS                                   BB_CHANINFO_TAB_B0_0_ADDRESS
#define BB_CHANINFO_TAB_B0_0_HW_MASK                                 0xffffffff
#define BB_CHANINFO_TAB_B0_0_SW_MASK                                 0xffffffff
#define BB_CHANINFO_TAB_B0_0_HW_WRITE_MASK                           0xffffffff
#define BB_CHANINFO_TAB_B0_0_SW_WRITE_MASK                           0xffffffff
#define BB_CHANINFO_TAB_B0_0_RSTMASK                                 0x00000000
#define BB_CHANINFO_TAB_B0_0_RESET                                   0x00000000

// Skip 3204 (BB_CHANINFO_TAB_B0_1) - 35fc (BB_CHANINFO_TAB_B0_255) for brevity
// 0x36b0 (BB_TX_FIR_COEFF_MEM_0)
#define BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_MSB                       23
#define BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_LSB                       0
#define BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_MASK                      0x00ffffff
#define BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_GET(x)                    (((x) & BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_MASK) >> BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_LSB)
#define BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_SET(x)                    (((0 | (x)) << BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_LSB) & BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_MASK)
#define BB_TX_FIR_COEFF_MEM_0_TX_FIR_COEFF_RESET                     0
#define BB_TX_FIR_COEFF_MEM_0_ADDRESS                                0x36b0
#define BB_TX_FIR_COEFF_MEM_ADDRESS                                  BB_TX_FIR_COEFF_MEM_0_ADDRESS
#define BB_TX_FIR_COEFF_MEM_0_HW_MASK                                0x00ffffff
#define BB_TX_FIR_COEFF_MEM_0_SW_MASK                                0x00ffffff
#define BB_TX_FIR_COEFF_MEM_0_HW_WRITE_MASK                          0x00000000
#define BB_TX_FIR_COEFF_MEM_0_SW_WRITE_MASK                          0x00ffffff
#define BB_TX_FIR_COEFF_MEM_0_RSTMASK                                0xff000000
#define BB_TX_FIR_COEFF_MEM_0_RESET                                  0x00000000

// Skip 36b4 (BB_TX_FIR_COEFF_MEM_1) - 397c (BB_TX_FIR_COEFF_MEM_179) for brevity
// 0x3980 (BB_TX_FIR_CNTL)
#define BB_TX_FIR_CNTL_TX_FIR_MCS_THR_MSB                            3
#define BB_TX_FIR_CNTL_TX_FIR_MCS_THR_LSB                            0
#define BB_TX_FIR_CNTL_TX_FIR_MCS_THR_MASK                           0x0000000f
#define BB_TX_FIR_CNTL_TX_FIR_MCS_THR_GET(x)                         (((x) & BB_TX_FIR_CNTL_TX_FIR_MCS_THR_MASK) >> BB_TX_FIR_CNTL_TX_FIR_MCS_THR_LSB)
#define BB_TX_FIR_CNTL_TX_FIR_MCS_THR_SET(x)                         (((0 | (x)) << BB_TX_FIR_CNTL_TX_FIR_MCS_THR_LSB) & BB_TX_FIR_CNTL_TX_FIR_MCS_THR_MASK)
#define BB_TX_FIR_CNTL_TX_FIR_MCS_THR_RESET                          0
#define BB_TX_FIR_CNTL_ADDRESS                                       0x3980
#define BB_TX_FIR_CNTL_HW_MASK                                       0x0000000f
#define BB_TX_FIR_CNTL_SW_MASK                                       0x0000000f
#define BB_TX_FIR_CNTL_HW_WRITE_MASK                                 0x00000000
#define BB_TX_FIR_CNTL_SW_WRITE_MASK                                 0x0000000f
#define BB_TX_FIR_CNTL_RSTMASK                                       0xffffffff
#define BB_TX_FIR_CNTL_RESET                                         0x00000000

// 0x8aac (BB_CHN_TABLES_DUMMY_1)
#define BB_CHN_TABLES_DUMMY_1_DUMMY1_MSB                             31
#define BB_CHN_TABLES_DUMMY_1_DUMMY1_LSB                             0
#define BB_CHN_TABLES_DUMMY_1_DUMMY1_MASK                            0xffffffff
#define BB_CHN_TABLES_DUMMY_1_DUMMY1_GET(x)                          (((x) & BB_CHN_TABLES_DUMMY_1_DUMMY1_MASK) >> BB_CHN_TABLES_DUMMY_1_DUMMY1_LSB)
#define BB_CHN_TABLES_DUMMY_1_DUMMY1_SET(x)                          (((0 | (x)) << BB_CHN_TABLES_DUMMY_1_DUMMY1_LSB) & BB_CHN_TABLES_DUMMY_1_DUMMY1_MASK)
#define BB_CHN_TABLES_DUMMY_1_DUMMY1_RESET                           0
#define BB_CHN_TABLES_DUMMY_1_ADDRESS                                0x8aac
#define BB_CHN_TABLES_DUMMY_1_HW_MASK                                0xffffffff
#define BB_CHN_TABLES_DUMMY_1_SW_MASK                                0xffffffff
#define BB_CHN_TABLES_DUMMY_1_HW_WRITE_MASK                          0x00000000
#define BB_CHN_TABLES_DUMMY_1_SW_WRITE_MASK                          0xffffffff
#define BB_CHN_TABLES_DUMMY_1_RSTMASK                                0x00000000
#define BB_CHN_TABLES_DUMMY_1_RESET                                  0x00000000


#endif /* _CHN_TABLE_MAP_H_ */
